Novel processing systems are increasingly relying on photonics to increase performance, reduce latency and improve efficiency in computation-intensive applications.
At the intra-chip level, Photonic Integrated Chips (PICs) provide a modern and improved alternative to ASICs for applications such as neuromorphic computing or machine learning. IDLab researches programmable photonic interconnect network architectures to enable general purpose PICs forming the photonic equivalent of FPGAs. This involves novel node architectures, routing schemes as well as dimensioning aspects of photonic integrated circuit interconnects.
Photonic network interconnects are also investigated at the inter-chip level. Photonic Network-on-Wafer (NoW) processing unit architectures are being investigated to overcome fundamental limitations in electrical interconnect scaling by implementing the inter chip network in a wafer-scale optical interposer. NoW design architecture, routing and overall dimensioning are topics which IDLab investigates to improve next-generation GPUs, TPUs and NPUs.
High Performance Computing (HPC) is the key platform executing the training of massive machine learning models empowering for example (chat)GPT. IDLab is researching network interconnect architectures and resource management strategies for HPC systems to enable efficient execution of multiple massive workloads avoiding bottlenecks in the network.
